Kludge Tracker: Gnuradio - v3.4.0-101-g7e2b45b

Kludge Summary of gnuradio/usrp/firmware/include

All Directories within gnuradio/usrp/firmware/include

All Files within gnuradio/usrp/firmware/include

• gnuradio/usrp/firmware/include/fpga_regs_standard.h (2)
• gnuradio/usrp/firmware/include/fpga_regs_standard.v (2)
• gnuradio/usrp/firmware/include/syncdelay.h (2)

Kludge Snippets in gnuradio/usrp/firmware/include

gnuradio/usrp/firmware/include/fpga_regs_standard.h — 1

181        // Possible future values of WIDTH = {4, 2, 1}
182        // 12 takes a bit more work, since we need to know packet alignment.
183        
184        // ------------------------------------------------------------------------
185        // FIXME register numbers 50 to 63 are available
186        
187        // ------------------------------------------------------------------------
188        // Registers 64 to 95 are reserved for user custom FPGA builds.
189        // The standard USRP software will not touch these.
				

gnuradio/usrp/firmware/include/fpga_regs_standard.h — 2

265        // still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
266        // The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
267        #define bitnoFR_RX_SYNC_INPUT_IOPIN		15
268        #define bmFR_RX_SYNC_INPUT_IOPIN		(1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
269        //TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
270        #define bitnoFR_RX_SYNC_OUTPUT_IOPIN	15
271        #define bmFR_RX_SYNC_OUTPUT_IOPIN	(1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
272        // =======================================================================
273        // READBACK Registers
				

gnuradio/usrp/firmware/include/fpga_regs_standard.v — 1

153        // Possible future values of WIDTH = {4, 2, 1}
154        // 12 takes a bit more work, since we need to know packet alignment.
155        
156        // ------------------------------------------------------------------------
157        // FIXME register numbers 50 to 63 are available
158        
159        // ------------------------------------------------------------------------
160        // Registers 64 to 95 are reserved for user custom FPGA builds.
161        // The standard USRP software will not touch these.
				

gnuradio/usrp/firmware/include/fpga_regs_standard.v — 2

228        // still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
229        // The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
230        `define bitnoFR_RX_SYNC_INPUT_IOPIN 15
231        `define bmFR_RX_SYNC_INPUT_IOPIN  (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
232        //TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
233        `define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
234        `define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
235        // =======================================================================
236        // READBACK Registers
				

gnuradio/usrp/firmware/include/syncdelay.h — 1

22        #ifndef _SYNCDELAY_H_
23        #define _SYNCDELAY_H_
24        
25        /*
26         * Magic delay required between access to certain xdata registers (TRM page 15-106).
27         * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles.  Each
28         * NOP is a single cycle....
29         *
30         * From TRM page 15-105:
				

gnuradio/usrp/firmware/include/syncdelay.h — 2

55         *	GPIFTCB1			GPIFTCB0
56         */
57        
58        /*
59         * FIXME ensure that the peep hole optimizer isn't screwing us
60         */
61        #define	SYNCDELAY	_asm nop; nop; nop; _endasm
62        #define	NOP		_asm nop; _endasm
63